1. Field of the Invention
The present invention relates to a memory cell architecture which includes a redundancy mechanism for repairing defective memory cells.
2. Description of Related Art
FIG. 1 is a schematic diagram of a conventional five transistor memory cell 100. Memory cell 100 includes n-channel access transistor 101, and inverters 102 and 103. Inverters 102 and 103 are cross-coupled to form a latch. Inverter 102 provides an output signal Q to output terminal 131. Memory cell 100 can be latched in either a logic low state (Q=logic low) or a logic high state (Q=logic high). The drain of access transistor 101 is coupled to receive an input signal D on input terminal 121. The gate of access transistor 101 is coupled to receive a control signal ADDR on input terminal 122. The source of access transistor 101 is coupled to the input terminal of inverter 102 and the output terminal of inverter 103.
Memory cell 100 is programmed by asserting a logic high control signal ADDR on input terminal 122, while controlling the input signal D applied to input terminal 121 to have either a logic high voltage level (e.g., V.sub.CC or 5 volts), or a logic low voltage level (e.g., V.sub.SS or 0 volts.) with sufficient strength to overcome inverter 103. When the input signal D has a logic low voltage level, memory cell 100 is programmed in a logic high state. Conversely, when the input signal D has a logic high level, memory cell 100 is programmed in a logic low state.
Memory cell 100 is commonly used as a configuration memory cell which stores a configuration bit in a field programmable gate array (FPGA). In general, output terminal 131 of memory cell 100 is connected to a control point of the FPGA (not shown). This control point can be, for example, the gate electrode of a pass transistor. The state of memory cell 100 determines whether the pass transistor is turned on, thereby completing a programmable connection between two different elements of the FPGA, or turned off, thereby isolating two different elements of the FPGA. If memory cell 100 is defective, the configuration of the FPGA can also be defective.
FIG. 2 is a schematic diagram of a conventional six transistor memory cell 200. Memory cell 200 is similar to memory cell 100. Thus, similar elements in memory cells 100 and 200 are labeled with similar reference numbers. In addition to the previously described elements of memory cell 100, memory cell 200 includes a second access transistor 201, which is coupled between output terminal 131 and input terminal 221.
In memory cell 200, the gate electrode of second access transistor 201 is coupled to receive the control signal ADDR. When the state of memory cell 200 is to be programmed, the control signal ADDR is asserted to turn on both of the access transistors 101 and 201. A logic low voltage is then applied to the drain of one of the transistors 101 and 201, and a logic high voltage is applied to the drain of the other of transistors 101 and 201. Like memory cell 100, memory cell 200 can be used as a configuration memory cell in an FPGA. Defects in either of memory cells 100 or 200 can result in a defective FPGA. Known methods for repairing defective memory cells typically require extensive redundant routing resources, thereby undesirably expanding the layout area and increasing routing congestion within the FPGA. One such redundancy scheme is described in "Node-Covering Based Defect and Fault Tolerance Methods for Increased Yield in FPGAs" by Hanchek and Dutt, Proceedings of the Ninth International Conference on VLSI Design, January 1996.
It would therefore be desirable to have a redundancy mechanism for replacing defective configuration memory cells within an FPGA, without significantly increasing the routing congestion or required layout area of the FPGA.